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max16963 dual 2.2mhz, low-voltage step-down dc-dc converter general description the max16963 is a high-efficiency, dual synchronous step-down converter that operates with a 2.7v to 5.5v input voltage range and provides a 0.8v to 3.6v output voltage range. the device delivers up to 1.5a of load current per output. the low input/output voltage range and the ability to provide high output currents make this device ideal for on-board point-of-load and postregulation applications. the device achieves q 3% output error over load, line, and temperature ranges. the device features a 2.2mhz fixed-frequency pwm mode for better noise immunity and load transient response, and a skip mode for increased efficiency during light-load operation. the 2.2mhz frequency operation allows for an all-ceramic capacitor design and small-size external components. an optional spread-spectrum frequency modulation minimizes radiated electromagnetic emissions due to the switching frequency. on-board low r dson switches help minimize efficiency losses at heavy loads and reduce critical/parasitic induc - tance, making the layout a much simpler task with respect to discrete solutions. following a simple layout and footprint ensures first-pass success in new designs. the device is offered in a factory-preset output voltage or adjustable output-voltage version (see the selector guide for options). factory-preset output-voltage versions allow customers to achieve q 3% output-voltage accuracy without using external resistors, while the adjustable output-voltage version provides the flexibility to set the output voltage to any desired value between 0.8v and 3.6v using an external resistive divider. additional features include 8ms fixed soft-start, 16ms fixed power-good delay, overcurrent, and overtemperature protections. the max16963 is available in thermally enhanced 16-pin tssop-ep and 4mm x 4mm, 16-pin tqfn-ep packages, and is specified for operation over the -40 n c to +125 n c automotive temperature range. applications automotive postregulationindustrial/military point-of-load applications benefits and features s small size components ? dual 2.2mhz dc-dc converter s ideal for point-of-load applications ? up to 1.5a output current ? adjustable output voltage: 0.8v to 3.6v ? 2.7v to 5.5v operating supply voltage s high efficiency at light load ? skip mode with 36a quiescent current s low electromagnetic emission ? programmable sync i/o pin ? spread spectrum s low power mode saves energy ? independent enable inputs s output rail monitoring helps prevent system failure ? open-drain power-good output s limits inrush current during startup ? built-in soft-start timer s overtemperature and short-circuit protections s 4mm x 4mm, 16-pin tqfn and 16-pin tssop packages s -40 n c to 125 n c operating temperature range typical application circuit 19-6487; rev 5; 7/15 ordering information appears at end of data sheet. evaluation kit available max16963 outs1 pv1 lx1 pgnd1 pg1 ep 2.2h 22f 20k 10 4.7f 1f v pv1 v out1 en1 gndpg2 pv v pv v out2 20k v out1 outs2 lx2 pgnd2 1.5h 22f v out2 pv2 4.7f v pv2 en2 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maximintegrated.com. downloaded from: http:///
2 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter pv, pv1, pv2 to gnd .............................................. -0.3v to +6v en1, en2, pg1, pg2 to gnd ................................. -0.3v to +6v lx_ current ........................................................... 1.6 (note 1) pgnd1 and pgnd2 to gnd .............................. -0.3v to +0.3v pv to pv1 and pv2 ............................................... -0.3v to +0.3v lx1 and lx2 continuous rms current ................................... 1a all other pins voltages to gnd .. (v pv + 0.3v) to (v gnd - 0.3v) output short-circuit duration .................................... continuous continuous power dissipation (t a = +70 n c) tqfn (derate 25mw/ n c above +70 n c)................... 2000mw* tssop (derate 26.1mw/ n c above +70 n c)........... 2088.8mw* operating temperature range ........................ -40 n c to +125 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-ambient thermal resistance ( b ja ) .......... 40 n c/w junction-to-case thermal resistance ( b jc ) ................. 6 n c/w tssop junction-to-ambient thermal resistance ( b ja ) ....... 38.3 n c/w junction-to-case thermal resistance ( b jc ) ................. 3 n c/w absolute maximum ratings note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 2) electrical characteristics (v pv = v pv1 = v pv2 = 5v, v en_ = 5v, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 3) * as per jedec51 standard (multilayer board). note 1: lx_ has internal clamp diodes for pgnd_ and pv_. applications that forward bias these diodes should take care not to exceed the ic?s package power-dissipation limits. parameter symbol conditions min typ max units supply voltage range v pv normal operation 2.7 5.5 v supply current i pv no load, v pwm = 0v 16 36 60 f a shutdown supply current i shdn v en1 = v en2 = 0v, t a = +25 c 1 5 f a undervoltage lockout threshold low v uvlo_l 2.37 v undervoltage lockout threshold high v uvlo_h 2.6 v undervoltage lockout hysteresis 0.07 v synchronous step-down dc-dc converter 1 fb regulation voltage v outs1 800 mv feedback set-point accuracy v outs1 i load = 4% to 100% -3 0 +3 % i load = 0% -0.5 +2 +3 % pmos on-resistance r dson_p1 v pv1 = 5v, i lx1 = 0.4a 90 148 m i nmos on-resistance r dson_n1 v pv1 = 5v, i lx1 = 0.8a 68 128 m i maximum pmos current-limit threshold i limp1 1.95 2.35 3.15 a downloaded from: http:///
3 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter electrical characteristics ( continued) (v pv = v pv1 = v pv2 = 5v, v en_ = 5v, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units maximum output current i out1 (v out1 + 0.5v p v pv1 p 5.5v) (note 4) 1.5 a outs1 bias current i b_outs1 fixed output-voltage variants -1 +1 f a adjustable output variants -1 +1 lx1 leakage current i lx1_leak v pv1 = 6v, lx1 = pgnd1 or pv1 t a = +25 c -1 +1 f a t a = +125c -5 +5 minimum on-time t on_min 60 ns lx1 discharge resistance r lx1 v en1 = 0v, through the outs_ pin 15 24 55 i maximum short-circuit current 3.9 a synchronous step-down dc-dc converter 2 fb regulation voltage v outs2 800 mv feedback set-point accuracy v outs2 i load = 4% to 100% -3 0 +3 % i load = 0% +1 +2 +3 pmos on-resistance r dson_p2 v pv2 = 5v, i lx2 = 0.4a 90 148 m i nmos on-resistance r dson_n2 v pv2 = 5v, i lx2 = 0.8a 68 128 m i maximum pmos current-limit threshold i limp2 1.95 2.55 3.15 a maximum output current i out2 (v out2 + 0.5v p v in2 p 5.5v) (note 4) 1.5 a outs2 bias current i b_outs2 fixed output-voltage variants 1 2 5 f a adjustable output variants 1 lx2 leakage current i lx2_leak v pv2 = 6v, lx2 = pgnd2 or pv2 t a = +25 c -1 +1 f a t a = +125c -5 +5 minimum on-time t on_min 60 ns lx2 discharge resistance r lx2 v en2 = 0v, through the outs_ pin 15 24 55 i maximum short-circuit current 3.9 a oscillator oscillator frequency f sw 2.0 2.2 2.4 mhz spread spectrum d f/f spread spectrum enabled +6 % sync input frequency range f sync 50% duty cycle (note 5) 1.7 2.4 mhz thermal overloadthermal shutdown threshold 165 c thermal shutdown hysteresis 15 c power-good outputs (pg1, pg2) pg_ overvoltage threshold pg ovth percentage of nominal output 106 110 114 % pg_ undervoltage threshold pg uvth percentage of nominal output 89.5 92 94 % active timeout period 16 ms downloaded from: http:///
4 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter electrical characteristics ( continued) (v pv = v pv1 = v pv2 = 5v, v en_ = 5v, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 3) note 3: all limits are 100% production tested at +25c. limits over temperature are guaranteed by design. note 4: calculated value based on an assumed inductor ripple of 30%. note 5: for sync frequency outside (1.7, 2.4)mhz, contact the factory. parameter symbol conditions min typ max units undervoltage/overvoltage propagation delay 28 f s output high leakage current t a = +25 c 0.2 f a pg1 output low voltage 2.6v v pv1 5.5v, i sink = 3ma 0.4 v v pv1 = 1.2v, i sink = 100 f a 0.4 pg2 output low voltage 2.6v v pv2 5.5v, i sink = 3ma 0.4 v v pv2 = 1.2v, i sink = 100 f a 0.4 enable inputs (en1, en2) input voltage high v inh input rising 2.4 1.7 2.4 v input voltage low v inl input falling 0.5 0.85 0.5 v input hysteresis 0.85 v input current v en_ = high 0.1 1.0 2 f a pulldown resistor v en_ = low 50 100 200 k i digital inputs (sync, pwm) input voltage high v inh 1.8 v input voltage low v inl 0.4 v input voltage hysteresis 50 mv pulldown resistor 50 100 200 k i digital output (sync) sync output voltage low v ol i sink = 3ma 0.4 v sync output voltage high v oh v pv_ = 5v, i source = 3ma 4.2 v downloaded from: http:///
5 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter typical operating characteristics (v pv = v pv1 = 5v, v en1 = v en2 = 5v, v out1 = 3.3v, v out2 = 1.8v, t a = +25c, unless otherwise noted.) efficiency vs. load current (v out = 3.3v) max16963 toc01 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 v in = 5v pwm skip efficiency vs. load current (v out = 1.8v) max16963 toc02 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 v in = 5v pwm skip v out load regulation (pwm) max16963 toc03 i load (a) regulation (%) 1.25 1.00 0.75 0.50 0.25 -2.5 -2.0 -1.5 -1.0 -0.5 0 -3.0 0 1.50 v in = 5v v out = 3.3v t a = -40c t a = +25c t a = +125c v out1 load regulation (skip) max16963 toc04 i load (a) regulation (%) 1.25 1.00 0.75 0.50 0.25 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 -3.0 0 1.50 v in = 5v v out = 3.3v t a = -40c t a = +25c t a = +125c i pv vs. temperature (skip) max16963 toc07 temperature (c) i pv (a) 110 95 80 65 50 35 20 5 -10 -25 25 30 35 40 45 5020 -40 125 v pv = 5v v pwm = 0v v en1 = v en2 = v pv v out1 = v out2 = 0.8 v out line regulation (pwm) max16963 toc05 v pv (v) regulation (%) 5.1 4.7 3.1 3.5 3.9 4.3 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 -0.40 2.7 5.5 v out = 1.8v i load = 0.75a t a = +125c t a = -40c t a = +25c load-transient response (pwm) max16963 toc08 1.5a0.15a 0a 50mv/div v out ac-coupled i load 100s/div v out = 3.3v i pv vs. v pv (skip) max16963 toc06 v pv (v) i pv (a) 5.0 4.5 4.0 3.5 3.0 20 30 40 50 60 7010 2.5 5.5 v pwm = 0v v en1 = v en2 = v pv v out1 = v out2 = 0.8v t a = +125c t a = -40c t a = +25c f sw vs. temperature max16963 toc09 temperature (c) f sw (mhz) 110 95 65 80 -10 5 20 35 50 -25 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.202.00 -40 125 v in = 5v pwm modei load = 0a downloaded from: http:///
6 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter pin configurations pin descriptions pin name function tqfn tssop 1 3 lx2 converter #2 switching node. lx2 is high impedance when converter #2 is off. 2 4 pgnd2 converter #2 power ground 3 5 pgnd1 converter #1 power ground 4 6 lx1 converter #1 switching node. lx1 is high impedance when converter #1 is off. 5 7 pv1 converter #1 input supply. bypass pv1 with at least a 4.7 f f ceramic capacitor to pgnd1. 6 8 en1 converter #1 enable input. drive en1 high to enable converter #1. drive en1 low to disable converter #1. 7 9 outs1 converter #1 feedback input (adjustable output option only). connect an external resistive divider from v out1 to outs1 and gnd to set the output voltage. 8 10 pg1 out1 power-good output. open-drain output. pg1 asserts when v out1 drops by 8%. connect to a 10k i pullup resistor. 9 11 gnd ground 10 12 pwm pwm control input. drive pwm high to put converters in forced pwm mode. drive pwm low to put converters in skip mode. 11 13 sync factory-set sync input or output. as an input, sync accepts a 1.7mhz to 2.5hmz external signal. as an output, sync outputs a 90 phase-shifted signal with respect to internal oscillator. 1516 14 13 65 7 pgnd2 lx1 8 lx2 syncgnd pv 12 outs2 4 12 11 9 en2pv2 pg1outs1 en1 pv1 + pgnd1 pwm 3 10 pg2 tqfn-ep (4mm x 4mm) top view + tssop-ep 13 4 sync pgnd2 14 3 pv lx2 15 2 pg2 pv2 16 1 outs2 en2 10 7 pg1 pv1 11 6 gnd lx1 9 8 outs1 en1 12 5 pwm pgnd1 ep ep top view max16963 max16963 downloaded from: http:///
7 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter pin descriptions (continued) detailed description the max16963 is a high-efficiency, dual synchronous step-down converter that operates with a 2.7v to 5.5v input voltage range and provides a 0.8v to 3.6v output voltage range. the max16963 delivers up to 1.5a of load current per output and achieves q 3% output error over load, line, and temperature ranges.the device features a pwm input that, when set to logic-high, forces the max16963 into a fixed-frequency, 2.2mhz pwm mode. a logic-low at the pwm input enables the device to enter a low-power pulse frequency modulation mode (pfm) under light-load conditions. an optional spread-spectrum frequency modulation mini - mizes radiated electromagnetic emissions due to the switching frequency and a factory programmable syn - chronization i/o (sync) allows better noise immunity. on-board low r dson switches help minimize efficiency losses at heavy loads and reduce critical/parasitic inductance, making the layout a much simpler task with respect to discrete solutions. following a simple layout and footprint ensures first-pass success in new designs. the device is offered in factory-preset output volt - ages to allow customers to achieve q 3% output-voltage accuracy without using expensive q 1% resistors. in addition, the adjustable output-voltage versions can be set to any desired values between 0.8v to 3.6v using an external resistive divider. see the selector guide for available options. additional features include 8ms fixed soft-start, 16ms fixed power-good output, overcurrent, and overtempera - ture protections. see figure 1 . power-good output the max16963 features an open-drain power-good out - put that asserts when the output voltage drops 8% below the regulated voltage. pg_ remains asserted for a fixed 16ms timeout period after the output rises up to its regulat - ed voltage. connect pg_ to outs_ with a 10k i resistor. soft-start the max16963 includes an 8ms fixed soft-start time. soft-start time limits startup inrush current by forcing the output voltage to ramp up towards its regulation point. spread-spectrum option the max16963 featuring spread-spectrum (ss) opera - tion varies the internal operating frequency up by ss = 6% relative to the internally generated operating fre - quency of 2.2mhz (typ). this function does not apply to externally applied oscillation frequency. the internal oscillator is frequency modulated with a 6% frequency deviation. see the selector guide for available options. synchronization (sync) sync is a factory-programmable i/o. see the selector guide for available options. when sync is configured as an input, a logic-high on pwm enables sync to accept signal frequency in the range of 1.7mhz < f sync < 2.5mhz. when sync is configured as an output, a logic-high on pwm enables sync to output a 90 n phase- shifted signal with respect to internal oscillator. pin name function tqfn tssop 12 14 pv device supply voltage input. bypass with at least a 1 f f ceramic capacitor to gnd. in addition, connect a 10 i decoupling resistor between pv and the bypass capacitor. 13 15 pg2 out2 power-good output. open-drain output. pg2 asserts when v out2 drops by 8%. connect to a 10k i pullup resistor. 14 16 outs2 converter #2 feedback input (adjustable output option only). connect an external resistive divider from v out2 to outs2 and gnd to set the output voltage. 15 1 en2 converter #2 enable input. drive en2 high to enable converter #2. drive en2 low to disable converter #2. 16 2 pv2 converter #2 input supply. bypass pv2 with at least a 4.7 f f ceramic capacitor to pgnd2. ? ? ep exposed pad. connect ep to a large-area contiguous copper ground plane for effective power dissipation. do not use as the only ic ground connection. ep must be connected to gnd. downloaded from: http:///
8 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter figure 1. internal block diagram max16963 control logic step-down #1 skip current comp current-sense amp peak current comp ramp generator pmw comp power-good comp error amp fpwm p1-ok zero-crossing comp outs1 sync en1 p2-ok clk1 pv1 pv1lx1 pgnd1 pg1 pgnd1 clk1 clk1clk2 fpwm en2 p1-ok current lim comp soft-start generator v ref voltage reference th-sd feedback driver osc. main control logic trim bits v ref otp pv pgnd1 pg2gnd control logic step-down #2 skip current comp current-sense amp peak current comp ramp generator pmw comp power-good comp error amp fpwm p2-ok zero-crossing comp outs1 clk2 pv1 pv2lx2 pgnd2 pgnd2 clk2 current lim comp soft-start generator v ref feedback driver pv pgnd2 downloaded from: http:///
9 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter current-limit/short-circuit protection the max16963 features current limit that protects the device against short-circuit and overload conditions at an output. in the event of a short-circuit or overload condi - tion at an output, the high-side mosfet remains on until the inductor current reaches the high-side mosfet?s current-limit threshold. the converter then turns on the low-side mosfet and the inductor current ramps down. the converter allows the high-side mosfet to turn on only when the inductor current ramps down to the low- side mosfet?s current threshold. this cycle repeats until the short or overload condition is removed. fpwm/skip modes the max16963 features an input (pwm) that puts the converter either in skip mode for forced pwm (fpwm) mode of operation. see the pin descriptions for mode detail. in fpwm mode, the converter switches at a con - stant frequency with variable on-time. in skip mode, the converter?s switching frequency is load-dependent until the output load reaches a certain threshold. at higher load current, the switching frequency does not change and the operating mode is similar to the fpwm mode. skip mode helps improve efficiency in light-load appli - cations by allowing the converters to turn on the high- side switch only when the output voltage falls below a set threshold. as such, the converter does not switch mosfets on and off as often as is the case in the fpwm mode. consequently, the gate charge and switching losses are much lower in skip mode. overtemperature protection thermal overload protection limits the total power dissi - pation in the max16963. when the junction temperature exceeds 165c (typ), an internal thermal sensor shuts down the internal bias regulator and the step-down controller, allowing the ic to cool. the thermal sensor turns on the ic again after the junction temperature cools by 15c. applications information adjustable output-voltage option the max16963 has an adjustable output voltage (see the selector guide for options) that allows the customer to set the outputs to any voltage between 0.8v and 3.6v. connect a resistive divider from output (v out_ ) to outs_ to gnd to set the output voltage ( figure 2 ). select r2 (outs_ to gnd resistor) less than or equal to 100k i . calculate r1 (v out_ to outs_ resistor) with the follow - ing equation: ?? ? ? = ? ?? ? ??? ?? ? ? ?? ? + out_ outs_ v r1 r2 1 v r1 r2 where 7.5k r1 r2 where v outs_ = 800mv (see the electrical characteristics table). the external feedback resistive divider must be frequency compensated for proper operation. place a capacitor across each resistor in the resistive divider network. use the following equation to determine the value of the capacitors: ?? = ???? r2 c1 1 0pf r1 connect outs_ to v out_ for the fixed output-voltage versions. inductor selection three key inductor parameters must be specified for operation with the max16963: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). use the following formulas to determine the mini - mum inductor value: ( ) ?? ?? ?? =? ?? ?? ?? ?? ?? ?? ?? out_ min1 in out_ in op ref cs v 3 l vv v fv g where f op is the operating frequency; this value is 2.2mhz, unless externally synchronized to a different frequency; v ref is the reference voltage equal to 1.25v; g cs is the internal current-sense conductance equal to 0.8. the next equation ensures that the inductor current down slope is less than the internal slope compensation. for figure 2. adjustable output voltage setting max16963 outs_ r1r2 c1 v out_ downloaded from: http:///
10 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter this to be the case, the following equation needs to be satisfied: ? m2 m 2 where m2 is the inductor current down slope: out v l and -m is the slope compensation: ? ref cs 0.8 v sg solving for l: = min2 out ref cs s lv 1.6 v g the equation that provides the bigger inductor value must be chosen for proper operation. = min min1 min2 l max(l , l ) then: = max min l 2l the maximum inductor value must not exceed the cal - culated value from the above formula. this ensures that the current feedback loop receives the correct amount of current ripple for proper operation. table 1 lists some of the inductor values for 1.5a output current and several output voltages. input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit?s switching. the input capacitor rms current requirement (i rms ) is defined by the following equation: ( ) out_ pv_ out_ rms load(max) pv_ v vv ii v ? = i rms has a maximum value when the input voltage equals twice the output voltage (v pv_ = 2v out_ ), so i rms(max) = i load(max) /2. choose an input capacitor that exhibits less than +10 n c self-heating temperature rise at the rms input current for optimal long-term reliability. the input-voltage ripple is composed of d v q (caused by the capacitor discharge) and d v esr (caused by the esr of the capacitor). use low-esr ceramic capacitors with high-ripple current capability at the input. assume the contribution from the esr and capacitor discharge equal to 50%. calculate the input capacitance and esr required for a specified input voltage ripple using the fol - lowing equations: esr in l out_ v esr i i 2 ? = ? + where: ( ) pv_ out_ out_ l pv_ sw vv v i v fl ? ?= and: out_ in q sw i d(1 d) c vf ? = ? and out_ pv_ v d v = where i out_ is the maximum output current, and d is the duty cycle. table 1. inductor values vs. (v in - v out ) v in - v out (v) 5.5 to 3.3 5.5 to 2.5 5.5 to 1.5 3.0 to 0.8 inductor (h), i load = 1.5a 1.5 1.5 1.0 0.68 downloaded from: http:///
11 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter output capacitor the minimum capacitor required depends on output voltage, maximum device current capability, and the error-amplifier voltage gain. use the following formula to determine the required output capacitor value: = = ? ref eamp out(min) co out cs out v xg c 2f v r 0.8v x 31.7 2 210khz v 378m where f co is the target crossover frequency equal to 210khz, g eamp is the error-amplifier voltage gain equal to 31.7v/v, and r cs is 378m . pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. use a multilayer board whenever possible for better noise immunity and power dissipation. follow these guidelines for good pcb layout: 1) use a large contiguous copper plane under the max16963 package. ensure that all heat-dissipating components have adequate cooling. the bottom pad of the max16963 must be soldered down to this copper plane for effective heat dissipation and maximizing the full power out of the max16963. use multiple vias or a single large via in this plane for heat dissipation. 2) isolate the power components and high current path from the sensitive analog circuitry. this is essential to prevent any noise coupling into the analog signals. 3) add small footprint blocking capacitors with low self- resonance frequency close to pv1, pv2, and pv. 4) keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. the high current path composed of input capacitors at pv1 and pv2, inductor, and the output capacitor should be as short as possible. 5) keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pcbs (2oz vs. 1oz) to enhance full-load efficiency. 6) outs_ are sensitive to noise for devices with external feedback option. the resistive network, r1, r2, and c1 must be placed close to outs_ and far away from the lx_ node and high switching current paths. the ground node of r2 must be close to gnd. 7) the ground connection for the analog and power section should be close to the ic. this keeps the ground current loops to a minimum. in cases where only one ground is used enough isolation between analog return signals and high power signals must be maintained. package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.co m/ packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos package type package code outline no. land pattern no. 16 tqfn-ep t1644+4 21-0139 90-0070 16 tssop-ep u16e+3 21-0108 90-0120 downloaded from: http:///
12 maxim integrated max16963 dual 2.2mhz, low-voltage step-down dc-dc converter ordering information /v denotes an automotive qualified part.+ denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. selector guide note: contact the factory for variants with different output voltage, spread spectrum, and power-good delay time settings. part temp range load current capability per output (a) pin-package max16963_ate_/v+ -40c to +125c 1.5/1.5 16 tqfn-ep* max16963_aue_/v+ -40c to +125c 1.5/1.5 16 tssop-ep* root part package suffix option suffix i load per output (a) output voltage spread spectrum sync in/ out power-good delay (ms) max16963 raue a/v+ 1.5/1.5 ext. adj. disabled in 16 max16963 saue a/v+ 1.5/1.5 ext. adj. enabled in 16 max16963 rate a/v+ 1.5/1.5 ext. adj. disabled in 16 max16963 sate a/v+ 1.5/1.5 ext. adj. enabled in 16 max16963 sate c/v+ 1.5/1.5 ext. adj. enabled out 16 max16963 sate d/v+ 1.5/1.5 ext. adj. enabled in 8 max16963 sate f/v+ 1.5/1.5 ext. adj. enabled out 8 downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 13 ? 2015 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max16963 dual 2.2mhz, low-voltage step-down dc-dc converter revision history revision number revision date description pages changed 0 11/12 initial release ? 1 9/13 updated input voltage high min spec and input voltage low max spec, figure 2, equation, step 6 in the pcb layout guidelines section, and the ordering information 4, 9, 11, 12 2 10/13 updated ordering information and added max16963sate/v+ and pg timing column to selector guide 12 3 2/14 added fb regulation voltage to the electrical characteristics table, corrected v out mismatch in the typical operating characteristic section, updated inductor selection and output capacitor sections, updated table 2, updated note in the selector guide 2, 3, 5, 9, 10, 12 4 4/14 updated v pv_ condition for pg_ output low voltage specification 4 5 7/15 added formula to equation in the setting the output voltage section, replaced the output capacitor section, and deleted table 2 9?11 downloaded from: http:///

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